The design is loosely based on a 6502 block diagram I found. This means that the ALU is used extensively, and that the instruction cycle count naturally matches the original 6502. Wherever it made sense I used the register names from the diagram. Unlike the NMOS 6502, the design is fully static and uses only a single clock. As a consequence, there is no time to fully register the address/data bus on input and output. Right now, I'm using block RAMs, so that's no problem. If you want to use external SRAM, it should be possible to register the outputs, but not the inputs (I haven't tried this yet, though). Note that the stack area (page 1) does back-to-back write cycles when doing JSR/BRK instructions. If you want to use external SRAM, these back-to-back writes need some care, since the WE# signal needs to be asserted and deasserted all in the same cycle. This should be possible by using DDR flipflop element, but I haven't tried it.
Note that while this implementation matches the 6502 with respect to instruction cycle time, it does not produce the exact same behaviour on the bus at every cycle. Because of the two-phase clock, the original 6502 could write the address on the first half of the cycle, and read the data on the second half. In my implementation, the address is written on cycle N, and the data is read on cycle N+1. This extra delay requires a slightly different pipeline. This only concerns the timing within an instruction. The total number of cycles for each instruction is still the same as the original.
Arlet Ottens (E-mail).
I also do freelance work (verilog, hardware, embedded software, linux), so if you need something different, let me know.
